The invention relates to a phase detector of the kind useful in phase lock loop (FLL) applications. Usually digital phase detectors are fed signals that are large with respect to the input noise so that noise performance is not significant. However, in many applications it has been found that responding to a signal that is accompanied by noise is required. In this instance it is desirable for the phase detector to respond in a linear fashion to the input signal amplitude. Thus, the phase detector output has an amplitude that is related to the input signal level as well as its phase with respect to a local clock signal.
The typical digital phase detector circuits provide performance that is dependent upon the type of circuit employed. The MM74HC4046 (formerly CD4046) is a commercially available CMOS phase lock loop IC. It includes a VCO and a phase detector and is intended for inclusion in a system where it is desired to lock a locally generated signal to an incoming signal at any frequency up to about 20 MHz. Since the performance of the phase detector is strongly dependent upon the kind of phase detector employed three different kinds are provided in the IC with the desired one user determined. The first phase detector is simply an XOR gate. It has the disadvantage of being susceptible to harmonic signal locking. The second phase detector is an edge sensitive digital sequential network that includes a three state output. This kind of phase detector is less likely to lock on harmonics, but is more noise sensitive. The third phase detector is an SR flip-flop gate and performs in a manner similar to that of the first phase detector. Typically, the user connects the desired detector to an external network that includes the PLL low pass filter that feeds the VCO.